AD9230-210EB 查看數據表（PDF） - Analog Devices
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AD9230-210EB Datasheet PDF : 21 Pages
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AD9230
Clock Input Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance
characteristics. The AD9230 contains a DCS (duty cycle
stabilizer) that retimes the non-sampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows
a wide range of clock input duty cycles without affecting the
performance of the AD9230. Noise and distortion performance
are nearly flat for a wide range duty cycles with the DCS on.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the non-sampling edge. As a result, any changes to the
sampling frequency require approximately TBD clock cycles to
allow the DLL to acquire and lock to the new rate.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated by
SNR =
20
log ⎢⎣⎡
π
2
f INPUT
×tJ
⎤
⎥⎦
In the equation, the rms aperture jitter represents the root-
mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
under-sampling applications are particularly sensitive to jitter,
see Figure 17.
75
0.2ps
70
65
0.5ps
60
1.0ps
55
1.5ps
2.0ps
50
2.5ps
3.0ps
45
40
1
10
100
1000
INPUT FREQUENCY (MHz)
Preliminary Technical Data
AD9230. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
POWER DISSIPATION AND POWER DOWN MODE
As shown in Figure 18 and Figure 20, the power dissipated by
the AD9230 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
Figure 18. AD9230-170, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
Figure 19. AD9230-210, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
Figure 17. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
Rev. PrE | Page 16 of 21
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