AD9230-11 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
比赛名单
AD9230-11 Datasheet PDF : 28 Pages
| |||
AD9230-11
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO)
Logic 0 Input Current (SDIO)
Logic 1 Input Current (SCLK, PWDN, CSB, RESET)
Logic 0 Input Current (SCLK, PWDN, CSB, RESET)
Input Capacitance
LOGIC OUTPUTS2
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Min
Typ
Max
Unit
0.2
AGND − 0.3
1.1
1.2
0
−10
−10
16
CMOS/LVDS/LVPECL
1.2
6
AVDD + 1.6
AVDD
3.6
0.8
+10
+10
20
24
4
V
V p-p
V
V
V
V
μA
μA
kΩ
pF
0.8 × AVDD
V
0.2 × AVDD
V
0
μA
−60
μA
55
μA
0
μA
4
pF
247
454
mV
1.125
1.375
V
Twos complement, gray code, or offset binary (default)
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. 0 | Page 5 of 28
Share Link: 