AD9238 查看數據表（PDF） - Analog Devices
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AD9238 Datasheet PDF : 48 Pages
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AD9238
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
Input Span = 1 V
Input Span = 2.0 V
ANALOG INPUT
Input Span = 1.0 V
Input Span = 2.0 V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Standby Power5
MATCHING CHARACTERISTICS
Offset Error
Gain Error
Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65
Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
Full VI
12
12
12
Bits
Full VI
Full VI
Full IV
Full V
25°C I
Full V
25°C I
12
12
12
Bits
±0.30 ±1.2
±0.50 ±1.1
±0.50 ±1.1 % FSR
±0.30 ±2.2
±0.50 ±2.4
±0.50 ±2.5 % FSR
±0.35
±0.35
±0.35
LSB
±0.35 ±0.9
±0.35 ±0.8
±0.35 ±1.0 LSB
±0.45
±0.60
±0.70
LSB
±0.40 ±1.4
±0.50 ±1.4
±0.55 ±1.75 LSB
Full V
±4
±4
±6
µV/°C
Full V
±12
±12
±12
ppm/°C
Full VI
Full V
Full V
Full V
±5
±35
0.8
±2.5
0.1
±5
±35
0.8
±2.5
0.1
±5 ±35 mV
0.8
mV
±2.5
mV
0.1
mV
25°C V
0.54
0.54
0.54
LSBrms
25°C V
0.27
0.27
0.27
LSBrms
Full IV
1
1
1
V p-p
Full IV
2
2
2
V p-p
Full V
7
7
7
pF
Full V
7
7
7
kΩ
Full IV
Full IV
Full V
Full V
Full V
Full V
Full VI
Full V
25°C V
25°C V
2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V
60
4
±0.01
110
10
±0.01
200
14
±0.01
mA
mA
% FSR
180
190 212
2.0
330
360 397
2.0
600
mW
640 698 mW
2.0
mW
±0.1
±0.05
±0.1
±0.05
±0.1
±0.05
% FSR
% FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 28 for the equivalent analog input structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
Rev. B | Page 4 of 48
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