AD9239 查看數據表（PDF） - Analog Devices
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AD9239 Datasheet PDF : 41 Pages
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AD9239
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 4.
Parameter1
CLOCK
Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
DATA OUTPUT PARAMETERS
Data Output Period or UI
(DOUT + x, DOUT − x)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)2
Pipeline Latency
Data Rate per Channel (NRZ)
Deterministic Jitter
Random Jitter
Channel-to-Channel Bit Skew
Channel-to-Channel Packet Skew3
Output Rise/Fall Time
TERMINATION CHARACTERISTICS
Differential Termination Resistance
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
OUT-OF-RANGE RECOVERY TIME
AD9239BCPZ-170
AD9239BCPZ-210
AD9239BCPZ-250
Temp Min Typ
Max Min Typ
Max Min Typ
Max Unit
Full 170
Full 2.65 2.9
Full 2.65 2.9
100 210
2.15 2.4
2.15 2.4
100 250
1.8 2.0
1.8 2.0
100 MSPS
ns
ns
Full
1/(16 × fCLK)
25°C
50
25°C
0.8
25°C
4
25°C
250
25°C
50
Full
40
25°C
2.72
25°C
10
25°C
6
25°C
0
25°C
+1
25°C
50
1/(16 × fCLK)
50
0.8
4
250
50
40
3.36
10
6
0
+1
50
1/(16 × fCLK)
50
0.8
4
250
50
40
4.0
10
6
0
+1
50
sec
%
UI
µs
ns
μs
CLK cycles
Gbps
ps max
ps rms
sec
CLK cycles
ps
25°C
100
100
100
Ω
25°C
1.2
1.2
1.2
ns
25°C
0.2
0.2
0.2
ps rms
25°C
1
1
1
CLK cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
2 Receiver dependent.
3 See the Digital Start-Up Sequence section.
Rev. E | Page 6 of 40
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