AD9251 查看數據表（PDF） - Analog Devices
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AD9251 Datasheet PDF : 37 Pages
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AD9251
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
Timing Diagrams
VIN
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
tDCO
tSKEW
N–9
N–8
N–7
tPD
Figure 2. CMOS Output Data Timing
Min
2
2
40
2
2
10
10
10
10
N+4
N–6
Typ
0.24
0.40
N+5
N–5
Max Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
N–1
tA
N
VIN
N+3
N+4
N+5
N+1
N+2
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
AS APPEARS ON
CH A OUTPUT PINS
tCH
tCLK
tDCO
tSKEW
CH A CH B
N–9 N–9
tPD
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
CH B
N–6
CH A
N–5
Figure 3. CMOS Interleaved Output Timing, Output as Appears on Channel A Output Pins
Rev. A | Page 8 of 36
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