AD9411(RevB) 查看數據表（PDF） - Analog Devices
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AD9411 Datasheet PDF : 28 Pages
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AD9411
Data Sheet
APPLICATION NOTES
The AD9411 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantiza-
tion by the 10-bit core. For ease of use, the part includes an on-
board reference and input logic that accepts TTL, CMOS, or
LVPECL levels. The digital output’s logic levels are LVDS
(ANSI-644) compatible.
Table 7. Output Select Coding1
S1 (Data Format
Select)
S5 (Full-Scale
Select)2
1
X
0
X
Mode
Twos Complement
Offset Binary
CLOCK INPUT
X
1
X
0
Full Scale = 0.768 V
Full Scale = 1.536 V
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track-and-
hold circuit is essentially a mixer, and any noise, distortion, or
timing jitter on the clock is combined with the desired signal at
the A/D output. For this reason, considerable care has been
E taken in the design of the clock inputs of the AD9411, and the
user is advised to give careful thought to the clock source.
The AD9411 has an internal clock duty cycle stabilization
T circuit that locks to the rising edge of CLK+ and optimizes
timing internally. This allows a wide range of input duty cycles
at the input without degrading performance. Jitter in the rising
E edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 30 MHz
nominally. The time constant associated with the loop should
L be considered in applications where the clock rate changes
dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase before valid data is available.
This circuit is always on and cannot be disabled by the user.
O The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
S MC100LVEL16 performs well in the circuit to drive the clock
inputs, as illustrated in Figure 39. Note that for this low voltage
PECL device, the ac coupling is optional.
B PECL
O GATE
0.1F
AD9411
CLK+
CLK–
1 X = Don’t Care.
2 S5 full-scale adjust (refer to the Analog Input section).
ANALOG INPUT
The analog input to the AD9411 is a differential buffer. For best
dynamic performance, impedances at VIN+ and VIN– should
match. The analog input is optimized to provide superior wide-
band performance and requires that the analog inputs be driven
differentially. SNR and SINAD performance degrades signifi-
cantly if the analog input is driven with a single-ended signal.
A wideband transformer, such as Mini-Circuits’ ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 2.8 V (refer to the Equivalent Circuits section). Note
that the input common-mode can be overdriven by
approximately +/−150 mV around the self-bias point, as shown
in Figure 42.
Special care was taken in the design of the analog input section
of the AD9411 to prevent damage and corruption of data when
the input is overdriven. The nominal differential input range is
approximately 1.5 V p-p ~ (768 mV × 2). Note that the best
performance is achieved with S5 = 0 (full-scale = 1.5). See
Figure 40 and Figure 41.
S5 = GND
VIN+
0.1F
510
510
768mV 2.8V
2.8V
Figure 39. Driving Clock Inputs with LVEL16
VIN–
DIGITALOUT = ALL 1s
DIGITALOUT = ALL 0s
Figure 40. Differential Analog Input Range
Rev. B | Page 18 of 28
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