AD9480(Rev0) 查看數據表（PDF） - Analog Devices

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AD9480
(Rev.:Rev0)

8-Bit, 250 MSPS 3.3 V A/D Converter

Analog Devices 

AD9480

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, unless otherwise noted.

Table 4.

Parameter

CLOCK

Maximum Conversion Rate

Minimum Conversion Rate

Clock Pulse Width High (tEH)

Clock Pulse Width Low (tEL)

OUTPUT PARAMETERS

Valid Time (tV)1

Propagation Delay (tPD)1

Rise Time (tR) 20% to 80%

Fall Time (tF) 20% to 80%

DCO Propagation Delay (tCPD)

Data-to-DCO Skew (tPD – tCPD)

Pipeline Latency

APERTURE

Aperture Delay (tA)

Aperture Uncertainty (Jitter)

Temp Test Level Min

Full

VI

250

Full

VI

Full

IV

1.2

Full

IV

1.2

Full

VI

1.9

Full

VI

Full

V

Full

V

Full

VI

1.9

Full

IV

0

25°C

VI

25°C

V

25°C

V

1 Valid Time is approximately equal to minimum tPD. CLoad equals 5 pF maximum.

AD9480-250

Typ

Max

20

2

2

2.8

3.8

0.5

0.5

2.7

3.7

0.1

0.6

8

1.5

0.25

Unit

MSPS

MSPS

ns

ns

ns

ns

ns

ns

ns

ns

Cycles

ns

ps rms

TIMING DIAGRAM

AIN

CLK+

CLK–

DATA

OUT

DCO+

DCO–

N–1

tA

N

tEH

tEL

N+1

8 CYCLES

1/fS

N+9

N+8

N+10

N+11

tCPD

tPD

N–8

tV

N–7

N

N+1

N+2

Figure 2. Timing Diagram

Rev. 0 | Page 6 of 28

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