AD9626-250EBZ 查看數據表（PDF） - Analog Devices

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产品描述 (功能)

比赛名单

AD9626-250EBZ

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter

Analog Devices 

TIMING DIAGRAMS

CLK+

CLK–

DCO–

DCO+

DAX

N+1

N+2

N

tA

tCLK = 1/fCLK

N+3

N+4

N+5

N+6

N+7

N+8

tCPD

tSKEW

tPD

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N

N+1 N+2

Figure 2. Single Port Mode

CLK+

CLK–

DCO+

DCO–

DAX

DBX

N+1 N+2

N

tA

tCLK = 1/fCLK

N+3

N+4

N+5

N+6

N+7

N+8

tCPDA

tCPDB

tPDA

tSKEWA

N–6

N–4

tSKEWB

N–2

N–7

tPDB

N–5

N–3

Figure 3. Interleaved Mode

N–1

N

N+2

N+1

AD9626

Rev. 0 | Page 7 of 36

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