AD9634-170EBZ 查看數據表（PDF） - Analog Devices
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AD9634-170EBZ Datasheet PDF : 31 Pages
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Data Sheet
AD9634
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS1
Input Clock Rate
Conversion Rate2
DCS Enabled
DCS Disabled
CLK Period, Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through
Divide-by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS1
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time (from Standby)
Wake-Up Time (from Power-Down)
Out-of-Range Recovery Time
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1 See Figure 2.
2 Conversion rate is the clock rate after the divider.
AD9634-170
AD9634-210
AD9634-250
Min Typ Max Min Typ Max Min Typ Max Unit
625
625
625 MHz
40
170 40
210 40
250 MSPS
10
170 10
210 10
250 MSPS
5.8
4.8
4
ns
2.61 2.9 3.19 2.16 2.4 2.64 1.8
2.76 2.9 3.05 2.28 2.4 2.52 1.9
0.8
0.8
0.8
1.0
1.0
0.1
0.1
2.0 2.2
2.0 2.1
1.0
0.1
ns
ns
ns
ns
ps rms
4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns
4.7 5.3 5.8 4.7 5.3 5.8 4.7 5.3 5.8 ns
0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns
10
10
10
Cycles
10
10
10
µs
100
100
100
µs
3
3
3
Cycles
Timing Diagram
VIN
CLK+
CLK–
DCO–
DCO+
D0±/D1±
EVEN/ODD (LSB)
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
tPD
D0
D1
N – 10 N – 10
D0
N–9
D1
N–9
D0
N–8
D1
N–8
D0
N–7
D1
N–7
D0
N–6
D10±/D11±
(MSB)
D10
D11
N – 10 N – 10
D10
N–9
D11
N–9
D10
N–8
Figure 2. Even/Odd LVDS Mode Data Output Timing
D11
N–8
D10
N–7
D11
N–7
D10
N–6
Rev. B | Page 7 of 30
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