AD9642-170EBZ 查看數據表（PDF） - Analog Devices

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AD9642-170EBZ

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)

Analog Devices 

Data Sheet

TIMING SPECIFICATIONS

Table 5.

Parameter

SPI TIMING REQUIREMENTS

tDS

tDH

tCLK

tS

tH

tHIGH

tLOW

tEN_SDIO

tDIS_SDIO

Test Conditions/Comments

See Figure 58 for SPI timing diagram

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge (not shown in Figure 58)

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge (not shown in Figure 58)

AD9642

Min Typ Max Unit

2

ns

2

ns

40

ns

2

ns

2

ns

10

ns

10

ns

10

ns

10

ns

Rev. B | Page 7 of 28

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