AD9643(RevE) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
比赛名单
AD9643
(Rev.:RevE)
(Rev.:RevE)
Analog Devices
AD9643 Datasheet PDF : 36 Pages
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AD9643
Data Sheet
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through
Divide-by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
LVDS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO-to-Data Skew (tSKEW)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time (from Standby)
Wake-Up Time (from Power-Down)
Out-of-Range Recovery Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9643-170
Min Typ Max
625
40
170
5.8
2.61 2.9
3.19
2.76 2.9
3.05
0.8
1.0
0.1
6.0
6.7
0.4
0.7
1.0
10
1.0
0.1
10
250
3
1 Conversion rate is the clock rate after the divider.
AD9643-210
Min Typ Max
625
40
210
4.8
2.16 2.4
2.64
2.28 2.4
2.52
0.8
1.0
0.1
6.0
6.7
0.4
0.7
1.0
10
1.0
0.1
10
250
3
AD9643-250
Min Typ Max
625
40
250
4
1.8
2.0
2.2
1.9
2.0
2.1
0.8
1.0
0.1
6.0
6.7
0.4
0.7
1.0
10
1.0
0.1
10
250
3
Unit
MHz
MSPS
ns
ns
ns
ns
ns
ps rms
ns
ns
ns
Cycles
ns
ps rms
µs
µs
Cycles
Rev. E | Page 8 of 36
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