AD9650 查看數據表（PDF） - Analog Devices

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AD9650

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Analog Devices 

VIN

CLK+

CLK–

DCOA/DCOB

CH A/CH B DATA

AD9650

N–1

tCH

tA

N

N+1

tCLK

N+2

N+3

N+4

N+5

tDCO

tSKEW

tPD

CH A CH B

N – 12 N – 12

CH A

N – 11

CH B

N – 11

CH A

N – 10

CH B

N – 10

CH A

N–9

CH B

N–9

CH A

N–8

Figure 4. LVDS Mode Data Output Timing

CLK+

SYNC

tSSYNC

tHSYNC

Figure 5. SYNC Input Timing Requirements

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