AD9629 查看數據表（PDF） - Analog Devices
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AD9629 Datasheet PDF : 33 Pages
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AD9629
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
DRVDD = 1.8 V
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
Temp
AD9629-20/AD9629-40/AD9629-65/AD9629-80
Min
Typ
Max
CMOS/LVDS/LVPECL
Full
0.9
Full
0.2
Full
GND − 0.3
Full
−10
Full
−10
Full
8
10
Full
4
3.6
AVDD + 0.2
+10
+10
12
Full
1.2
Full
0
Full
−50
Full
−10
Full
30
Full
2
DRVDD + 0.3
0.8
−75
+10
Full
1.2
Full
0
Full
−10
Full
40
Full
26
Full
2
DRVDD + 0.3
0.8
+10
135
Unit
V
V p-p
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
Full
3.29
Full
3.25
Full
Full
Full
1.79
Full
1.75
Full
Full
V
V
0.2
V
0.05
V
V
V
0.2
V
0.05
V
1 Internal 30 kΩ pull-down.
2 Internal 30 kΩ pull-up.
Rev. B | Page 6 of 32
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