EVAL-ADF4193EB1(RevB) 查看數據表（PDF） - Analog Devices

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EVAL-ADF4193EB1
(Rev.:RevB)

Low Phase Noise, Fast Settling PLL Frequency Synthesizer

Analog Devices 

INTERFACING

The ADF4193 has a simple SPI®-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When LE goes high, the 24 bits that have been clocked

into the input register on each rising edge of CLK are latched

into the appropriate register. See Figure 2 for the timing

diagram and Table 5 for the register address table.

The maximum allowable serial clock rate is 33 MHz.

ADuC812 Interface

Figure 37 shows the interface between the ADF4193 and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Some registers of the ADF4193

require a 24-bit programming word. This is accomplished by

writing three 8-bit bytes from the MicroConverter to the device.

When the third byte is written, the LE input should be brought

high to complete the transfer.

An I/O port line on the ADuC812 can also be used to detect

lock (MUXOUT configured as lock detect and polled by the

port input).

ADuC812

SCLOCK

MOSI

I/O PORTS

ADF4193

CLK

DATA

LE

MUXOUT

(LOCK DETECT)

Figure 37. ADuC812 to ADF4193 Interface

ADF4193

ADSP-21xx Interface

Figure 38 shows the interface between the ADF4193 and the

ADSP-21xx digital signal processor. The ADF4193 needs a

24-bit serial word for some writes. The easiest way to accom-

plish this using the ADSP-21xx family is to use the autobuffered

transmit mode of operation with alternate framing. This

provides a means for transmitting an entire block of serial data

before an interrupt is generated. Set up the word length for

eight bits and use three memory locations for each 24-bit word.

To program each 24-bit word, store the three 8-bit bytes, enable

the autobuffered mode, and then write to the transmit register

of the DSP. This last operation initiates the autobuffer transfer.

ADSP-21xx

SCLK

DT

TFS

ADF4193

CLK

DATA

LE

I/O FLAGS

MUXOUT

(LOCK DETECT)

Figure 38. ADSP-21xx to ADF4193 Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-32-3) are rectangular.

The printed circuit board (PCB) pad for these should be

0.1 mm longer than the package land length and 0.05 mm wider

than the package land width. The land should be centered on

the pad. This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the PCB should be at least as large as the

exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

Thermal vias can be used on the PCB thermal pad to improve

the thermal performance of the package. If vias are used, they

should be incorporated in the thermal pad at 1.2 mm pitch grid.

The via diameter should be between 0.3 mm and 0.33 mm, and

the via barrel should be plated with one ounce copper to plug

the via.

The user should connect the PCB thermal pad to AGND.

Rev. B | Page 27 of 28

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