ADG725 查看數據表（PDF） - Analog Devices
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ADG725 Datasheet PDF : 16 Pages
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PIN CONFIGURATIONS
48-Lead LFCSP and TQFP
ADG725/ADG731
48 47 46 45 44 43 42 41 40 39 38 37
S12A 1
S11A 2
S10A 3
S9A 4
S8A 5
S7A 6
S6A 7
S5A 8
S4A 9
S3A 10
S2A 11
S1A 12
PIN 1
IDENTIFIER
ADG725
TOP VIEW
(Not to Scale)
36 S12B
35 S11B
34 S10B
33 S9B
32 S8B
31 S7B
30 S6B
29 S5B
28 S4B
27 S3B
26 S2B
25 S1B
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
S12 1
S11 2
S10 3
S9 4
S8 5
S7 6
S6 7
S5 8
S4 9
S3 10
S2 11
S1 12
PIN 1
IDENTIFIER
ADG731
TOP VIEW
(Not to Scale)
36 S28
35 S27
34 S26
33 S25
32 S24
31 S23
30 S22
29 S21
28 S20
27 S19
26 S18
25 S17
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
ADG725 ADG731 Mnemonic Function
1–12, 25–40, 1–12, 25–40, Sxx
45–48
45–48
13, 14
13, 14
VDD
17
17
SYNC
18
18
19
19
23
23
24
24
41, 43
N/A
N/A
43
DIN
SCLK
GND
VSS
DA, DB
D
Source. May be an input or output.
Power Supply Input. These parts can be operated from a single supply of 1.8 V to 5.5 V
and a dual supply of ± 2.5 V.
Active Low Control Input. This is the frame synchronization signal for the input
data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input
Shift Register is enabled. An 8-bit counter is also enabled. Data is transferred on the
falling edges of the following clocks. After eight falling clock edges, switch conditions
are automatically updated. SYNC may be used to frame the signal or just pulled low
for a short period of time to enable the counter and input buffers.
Serial Data Input. Data is clocked into the 8-bit Input Register MSB first on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the Input Shift Register on the falling edge of
the serial clock input. These devices can accommodate serial input rates of up to 30 MHz.
Ground Reference
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications,
connect to GND.
Drain. May be an input or output.
Drain. May be an input or output.
REV. A
–7–
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