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ADG738

CMOS, Low Voltage, 3-Wire Serially-Controlled, Matrix Switches

Analog Devices 

Data Sheet

THEORY OF OPERATION

The ADG738 and ADG739 are serially controlled, 8-channel

and dual 4-channel matrix switches, respectively. While provid-

ing the normal multiplexing and demultiplexing functions,

these parts also provide the user with more flexibility as to

where their signal may be routed. Each bit of the 8-bit serial

word corresponds to one switch of the part. A Logic 1 in the

particular bit position turns on the switch, while a Logic 0 turns

the switch off. Because each switch is independently controlled

by an individual bit, this provides the option of having any, all,

or none of the switches on. This feature may be particularly

useful in the demultiplexing application where the user may

wish to direct one signal from the drain to a number of outputs

(sources). Take care, however, in the multiplexing situation

where a number of inputs may be shorted together (separated

only by the small on resistance of the switch).

When changing the switch conditions, a new 8-bit word is

written to the input shift register. Some of the bits may be the

same as the previous write cycle, as the user may not wish to

change the state of some switches. To minimize glitches on the

output of these switches, the part cleverly compares the state of

switches from the previous write cycle. If the switch is already

in the on condition, and is required to stay on, there will be

minimal glitches on the output of the switch.

POWER-ON RESET

During device power-up, all switches will be in the off condi-

tion and the internal input shift register is filled with zeros and

remains so until a valid write takes place.

SERIAL INTERFACE

The ADG738 and ADG739 have a 3-wire serial interface

(SYNC, SCLK, and DIN), which is compatible with SPI, QSPI,

MICROWIRE interface standards and most DSPs. Figure 3

shows the timing diagram of a typical write sequence.

Data is written to the 8-bit input shift register via DIN under

the control of the SYNC and SCLK signals. Data may be written

to the input shift register in more or less than eight bits. In each

case, the input shift register retains the last eight bits that were

written.

When SYNC goes low, the input shift register is enabled. Data

from DIN is clocked into the input shift register on each falling

edge of SCLK. Each bit of the 8-bit word corresponds to one of

the eight switches. Figure 26 shows the contents of the input

shift register. Data appears on the DOUT pin on the rising edge

of SCLK suitable for daisy-chaining, delayed, of course, by eight

bits. When all eight bits have been written into the shift register,

the SYNC line is brought high again. The switches are updated

with the new configuration and the input shift register is

disabled. With SYNC held high, any further data or noise

on the DIN line has no effect on the shift register.

ADG738/ADG739

DB7 (MSB)

DB0 (LSB)

S8 S7 S6 S5 S4 S3 S2 S1

DATA BITS

Figure 26. Input Shift Register Contents

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the ADG738/ADG739 is via

a serial bus that uses a standard protocol compatible with

microcontrollers and DSP processors. The communications

channel is a 3-wire (minimum) interface consisting of a

clock signal, a data signal, and a synchronization signal.

The ADG738/ADG739 requires an 8-bit data word with

data valid on the falling edge of SCLK.

Data from the previous write cycle is available on the DOUT

pin. The following sections illustrate simple 3-wire interfaces

with popular microcontrollers and DSPs.

ADSP-21xx TO ADG738/ADG739

An interface between the ADG738/ADG739 and the ADSP-

21xx is shown in Figure 27. In the interface example shown,

SPORT0 is used to transfer data to the matrix switch. The

SPORT control register should be configured as follows:

internal clock operation, alternate framing mode; active low

framing signal.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled. As the data is clocked out of

the DSP on the rising edge of SCLK, no glue logic is required to

interface the DSP to the matrix switch. The update of each switch

condition takes place automatically when TFS is taken high.

TFS

ADSP-21xx* DT

SCLK

SYNC

DIN ADG738/

ADG739

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 27. ADSP-21xx to ADG738/ADG739 Interface

Rev. A | Page 15 of 20

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