EVAL-ADN2806EB(Rev0) 查看數據表（PDF） - Analog Devices
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EVAL-ADN2806EB Datasheet PDF : 20 Pages
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ADN2806
Table 6. Internal Register Map1
Reg
Name R/W Addr D7
D6
D5
FREQ0 R 0x0 MSB
FREQ1 R 0x1 MSB
FREQ2 R 0x2 0
MSB
MISC R 0x4 x
x
x
CTRLA W
CTRLB W
CTRLC W
0x8
0x9
0x11
FREF range
Config Reset
LOL MISC[4]
0
0
System
reset
0
1 All writeable registers default to 0x00.
D4 D3
D2
D1
Static LOL
LOL status
Data rate
measurement
complete
Data rate/DIV_FREF ratio
0
Reset 0
MISC[2]
0
0
x
x
Measure data rate
0
SQUELCH mode
D0
LSB
LSB
LSB
x
Lock to reference
0
Output boost
Table 7. Miscellaneous Register, MISC
Static LOL
D7 D6 D5 D4
x
x
x
0 = Waiting for next LOL
1 = Static LOL until reset
LOL Status
D3
0 = Locked
1 = Acquiring
Data Rate Measurement Complete
D2
0 = Measuring data rate
1 = Measurement complete
D1 D0
x
x
Table 8. Control Register, CTRLA1
FREF Range
Data Rate/Div_FREF Ratio
D7 D6
D5 D4 D3 D2
0 0 19.44 MHz
0 1 0 1 32
0 1 38.88 MHz
0 1 0 1 32
1 0 77.76 MHz
0 1 0 1 32
1 1 155.52 MHz
0 1 0 1 32
Measure Data Rate
D1
Set to 1 to measure data rate
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
1 Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
D7
D6
0 = LOL pin normal operation Write a 1 followed
1 = LOL pin is static LOL
by 0 to reset MISC[4]
System Reset
D5
Write a 1 followed by
0 to reset ADN2806
D4
Set to 0
Reset MISC[2]
D3
Write a 1 followed
by 0 to reset MISC[2]
D2
D1
D0
Set to 0 Set to 0 Set to 0
Table 10. Control Register, CTRLC
D7
D6
D5
D4
D3
D2
Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0
SQUELCH Mode
D1
0 = Squelch data outputs and
clock outputs
1 = Squelch data outputs or
clock outputs
Output Boost
D0
0 = Default output swing
1 = Boost output swing
Rev. 0 | Page 9 of 20
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