ADN4664 查看數據表（PDF） - Analog Devices

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产品描述 (功能)

比赛名单

ADN4664

Dual, 3 V, CMOS, LVDS Differential Line Receiver

Analog Devices 

Test Circuits and Timing Diagrams

VCC

SIGNAL

GENERATOR

RINx+

RINx–

50Ω 50Ω

ROUTx

CL

RECEIVER IS

ENABLED

CL = LOAD AND TEST JIG CAPACITANCE

Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

RINx–

RINx+

0V (DIFFERENTIAL)

tPLHD

VID = 200mV

1.2V

tPHLD

80%

80%

1.3V

1.1V

VOH

ROUTx

1.5V

1.5V

20%

20%

tTLH

tTHL

VOL

Figure 3. Receiver Propagation Delay and Transition Time Waveforms

ADN4664

Rev. 0 | Page 5 of 12

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