ADP3168 查看數據表（PDF） - Analog Devices
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ADP3168 Datasheet PDF : 24 Pages
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6-Bit, Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3168
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
±10 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to
external high power drivers
Active current balancing between all output phases
Built-in Power Good/crowbar blanking supports
On-the-fly VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for:
Next generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP3168 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between
0.8375 V and 1.6 V, and uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation, allowing for the construc-
tion of up to four complementary buck switching stages.
The ADP3168 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3168 also provides accurate and
reliable short-circuit protection, adjustable current limiting, and
a delayed Power Good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The device is specified over the commercial temperature range
of 0°C to 85°C and is available in a 28-lead TSSOP package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ RT
14
13
ADP3168
11
EN
UVLO
SHUTDOWN
AND BIAS
19
GND DAC
+150mV
CSREF
DAC
–250mV
10
PWRGD
DELAY
15
ILIMIT
EN
12
DELAY
SOFT-
START
OSCILLATOR
CMP
SET EN
RESET
27
PWM1
CURRENT-
BALANCING
CIRCUIT
CMP RESET
26
2-, 3-, 4-PHASE PWM2
DRIVER LOGIC
CMP RESET
25
PWM3
CMP RESET
CROWBAR
CURRENT
LIMIT
CURRENT-
LIMIT
CIRCUIT
24
PWM4
23
SW1
22
SW2
21
SW3
20
SW4
17
CSSUM
16
CSREF
18
CSCOMP
9
COMP
8
FB
PRECISION
REFERENCE
VID
DAC
7
FBRTN
1
2
3
4
5
6
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
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