ADP3208D 查看數據表（PDF） - ON Semiconductor

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ADP3208D

7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller

ON Semiconductor 

ADP3208D

Pin No

31

32

33

34

35

36

Mnemonic

PGND1

DRVL1

PVCC1

SW1

DRVH1

BST1

37

38

39 to

45

46

47

VCC

SP

VID6 to

VID0

PSI

DPRSTP

48

DPRSLP

Description

Low−Side Driver Power Ground for Phase 1.

Low−Side Gate Drive Output for Phase 1.

Power Supply Input/Output of Low−Side Gate Driver for Phase 1.

Current Balance Input for Phase 1 and Current Return For High−Side Gate Drive.

High−Side Gate Drive Output for Phase 1.

High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage

while the high−side MOSFET is on.

Power Supply Input/Output of the Controller.

Single−Phase Select Input. Logic high state sets single−phase configuration.

Voltage Identification DAC Inputs. A 7−bit word (the VID code) programs the DAC output voltage, the

reference voltage of the voltage error amplifier without a load (see the VID code Table 3).

Power State Indicator Input. Driving this pin low forces the controller to operate in single−phase mode.

Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the DPRSLP

pin; however, during slow deeper sleep exit, both pins are logic low.

Deeper Sleep Control Input.

EN 1

PWRGD

NC

CLKEN

FBRTN

FB

COMP

NC

IRPM/NC

VARFREQ

VRTT

TTSNS

ADP3208D

BST1

DRVH1

SW1

PVCC1

DRVL1

PGND1

PGND2

DRVL2

PVCC2

SW2

DRVH2

BST2

Figure 5. Pin Configuration

(Top View)

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