ADT7320 查看數據表（PDF） - Analog Devices
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ADT7320 Datasheet PDF : 25 Pages
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ADT7320
Data Sheet
Parameter
Shutdown Current
At 3.3 V
At 5.5 V
Power Dissipation, Normal Mode
Power Dissipation, 1 SPS Mode
Min
Typ
Max Unit Test Conditions/Comments
Supply current in shutdown mode
2.0
15
µA
5.2
25
µA
700
µW VDD = 3.3 V, normal mode at 25°C
150
µW Power dissipated for VDD = 3.3 V, TA = 25°C
1 Accuracy specification includes repeatability.
2 The equivalent 3 σ limits are ±0.15°C. This 3 σ specification is provided to enable comparison with other vendors who use these limits.
3 For higher accuracy at 5 V operation, contact Analog Devices, Inc.
4 Temperature hysteresis does not include repeatability.
5 Based on a floating average of 10 readings.
6 Drift includes solder heat resistance and lifetime test performed as per JEDEC Standard JESD22-A108.
SPI TIMING SPECIFICATIONS
TA = −40°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns
(10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2.
Parameter1, 2
t1
t2
t3
t4
t5
t6
t7 3
t8
t9
t10
Limit at TMIN, TMAX
0
100
100
30
25
5
60
80
10
80
0
0
60
80
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns min
Descriptions
CS falling edge to SCLK active edge setup time
SCLK high pulse width
SCLK low pulse width
Data setup time prior to SCLK rising edge
Data hold time after SCLK rising edge
Data access time after SCLK falling edge
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS rising edge hold time
CS falling edge to DOUT active time
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
SCLK inactive edge to DOUT low
1 Sample tested during initial release to ensure compliance.
2 See Figure 2.
3 This means that the times quoted in the timing characteristics in Table 2 are the true bus relinquish times of the part and, as such, are independent of external bus
loading capacitances.
CS
SCLK
DIN
DOUT
t1
t2
t3
1
2
3
t4
t5
MSB
6
7
8
9
10
LSB
t9
t6
MSB
Figure 2. Detailed SPI Timing Diagram
t8
23
24
t10
LSB
t7
Rev. 0 | Page 4 of 24
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