AIC1384GSHTB 查看數據表（PDF） - Analog Intergrations
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AIC1384GSHTB Datasheet PDF : 15 Pages
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AIC1384
device is not available. Use vias to lead the
heat into the buried layer.
4. The input capacitor should be placed as
close as possible to the PVIN pin.
5. A bypass capacitor, located close to the
VREF pin, can be used to improve
performance. Ranging from 0.01µF to 0.1µF
of ceramic capacitor is recommended.
6. If long sense traces is used, the noise of
VSENSE trace may occurs which from
switching I/O signals. A 0.1uF ceramic
capacitor connects to the VSENSE pin can be
used to filter high frequency signal.
APPLICATION EXAMPLES
DDRⅠ Application
1
GND
VTT
8
SD
2
SD
PVIN
7
3
VSENSE AVIN
6
VREF=1.25V
4
VREF
AIC1384
10nF
VDDQ
5
VDDQ=2.5V
VTT=1.25V
Cout
VIN=2.5V
Cin
All the input rails connect to 2.5V rail is
recommend for the SSTL-2 termination scheme
application. The circuitry completes an optimal
power dissipation and component count.
1
GND
VTT
8
SD
2
SD
PVIN
7
3
VSENSE AVIN
6
VREF=1.25V
4
VREF
AIC1384
10nF
VDDQ
5
VDDQ=2.5V
VTT=1.25V
Cout
VIN=3.3V
Cin
Connect the AIC1384 power rail to 3.3V to provide
the maximum continuous output current if 1.8V and
2.5V rail are not available. Beware the junction
temperature to exceed the maximum due to large
current level. In this configuration AVIN will be
limited to operation on the 3.3V or 5V rail results
from PVIN can never exceed AVIN.
VTT=1.25V
Cout
1
GND
VTT
8
SD
2
SD
PVIN
7
1.8V
3
VSENSE AVIN
6
2.2~5.5V
VREF=1.25V
4
VREF VDDQ
5
Cin
0.1uF
AIC1384
VDDQ=2.5V
10nF
AVIN and PVIN have the ability to work with
separate supplies. PVIN can be operated on a
lower 1.8V rail and the AVIN can be connected to a
higher rail. Although this circuitry can obtain better
efficiency, but the maximum continuous current is
reduced due to the lower rail voltage. Increasing
the output capacitance can also help for large load
transients.
12
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