AIC1384GSTB 查看數據表（PDF） - Analog Intergrations

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AIC1384GSTB

DDR Termination Regulator

Analog Intergrations 

AIC1384

DDRⅡ Application

VTT=0.9V

Cout

1

GND

VTT

8

SD

2

SD

PVIN

7

1.8V

3

VSENSE AVIN

6

2.2~5.5V

VREF=0.9V

4

VREF VDDQ

5

Cin

0.1uF

AIC1384

VDDQ=1.8V

10nF

The circuit is recommended for DDR-II applications.

The output stage is connected to the 1.8V rail and

the AVIN pin can be connected to either a 3.3V or

5V rail.

1

GND

VTT

8

SD

2

SD

PVIN

7

3

VSENSE AVIN

6

VREF=0.9V

4

VREF

AIC1384

10nF

VDDQ

5

VDDQ=1.8V

VTT=0.9V

Cout

VIN=3.3V

Cin

Connect the power rail to 3.3V to provide a higher

continuous output current if 1.8V rail is not

available. Careful with the junction temperature

that may exceed the maximum due to the thermal

dissipation increases with lower VTT output

voltages. In this configuration PVIN will be limited

to operation on the 3.3V rail.

Level Shifting Application

VTT

Cout

1

GND

VTT

8

R1 2

SD

PVIN

7

VIN

3

VSENSE AVIN

6

R2 4

VREF VDDQ

5

Cin

AIC1384

VDDQ

The AIC1384 is available to scale the output to any

voltage required. One method is to level shift the

output above the internal reference voltage of

VDDQ/2 by using two resistors from the VTT to the

VSENSE. The correct voltage at VTT is

VTT = VDDQ/2 (1 + R1/R2)

1

GND

VTT

8

R1

2

SD

PVIN

7

3

VSENSE AVIN

6

R2

4

VREF VDDQ

5

AIC1384

VDDQ

VTT

Cout

VIN

Cin

Another method is to level shift the output below

the internal reference voltage of VDDQ/2 by using

two resistors from the VSENSE and VDDQ. The

correct voltage at VTT is

VTT = VDDQ/2 (1 - R1/R2)

13

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