AIC1571 查看數據表（PDF） - Analog Intergrations

零件编号

产品描述 (功能)

比赛名单

AIC1571

5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers

Analog Intergrations 

AIC1571

component selection and tight layout of critical

components, and short, wide metal trace mini-

mize the voltage spike.

1) A ground plane should be used. Locate the

input capacitors (CIN) close to the power

switches. Minimize the loop formed by CIN,

the upper MOSFET (Q1) and the lower

MOSFET (Q2) as possible. Connections

should be as wide as short as possible to

minimize loop inductance.

2) The connection between Q1, Q2 and out-

put inductor should be as wide as short as

practical. Since this connection has fast

voltage transitions will easily induce EMI.

3) The output capacitor (COUT) should be lo-

cated as close the load as possible. Be-

cause minimize the transient load magni-

tude for high slew rate requires low induc-

tance and resistance in circuit board

4) The AIC1571 is best placed over a quiet

ground plane area. The GND pin should be

+12V

+

connected to the groundside of the output

capacitors. Under no circumstances should

GND be returned to a ground inside the CIN,

Q1, Q2 loop. The GND and PGND pins

should be shorted right at the IC. This help

to minimize internal ground disturbances in

the IC and prevents differences in ground

potential from disrupting internal circuit op-

eration.

5) The wiring traces from the control IC to the

MOSFET gate and source should be sized

to carry 1A current. Locate COUT2 close to

the AIC1571 IC.

6) The Vcc pin should be decoupled directly to

GND by a 1uF ceramic capacitor, trace

lengths should be as short as possible.

+3.3VIN

+

Q3

VOUT3

+

COUT3

Q4

VOUT2

+

COUT2

Css

VCC

VIN2

GATE3

GATE2

SS

GND

OCSET

UGATE

PHASE

LGATE

PGND

+5VIN

+

Q1

CIN

LOUT

+

VOUT

COUT

Q2

Power Plane Layer

Circuit Plane Layer

Via Connection to Ground Plane

Fig. 18 Printed circuit board power planes and islands

A multi-layer printed circuit board is recom-

mended. Figure 18 shows the connections of

the critical components in the converter. The

CIN and COUT could each represent numerous

physical capacitors. Dedicate one solid layer for

a ground plane and make all critical component

ground connections with vias to this layer.

13

Share Link: