(5) Power Up sequence
There are no order restriction to make power up, AVDD, DVDD, PVDD1, PVDD2.
Clock input is not necessary to write register.
(5-1) The sequence for power down mode after power-up.
Clock input to the CLKIN pin is necessary to guarantee “Current Consumption of Power down”
(r) : Register-bit
[AK8825]
Power
Supply
PDN
CLKIN
DTRSTN (r)
PLLPDN (r)
CONVMOD[1:0] (r)
t >100ns(Note.1)
t >100clk
Low
0x00 (Composite Video Encoder mode)
AVDD:2.7V
DVDD:1.65V
PVDD:1.65V
Fig. 12 Power-Up sequence (To make Power down state after power-up)
Note.1) Please wait 100ns for make PDN pin low after the Voltage of Power Supply becomes stable enough,
Rev-E-00
20
2008/03