HM5225645F 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HM5225645F

256M LVTTL interface SDRAM 100 MHz 1-Mword × 64-bit × 4-bank/2-Mword × 32-bit × 4-bank PC/100 SDRAM

Hitachi -> Renesas Electronics 

HM5225645F-B60, HM5225325F-B60

Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the

output open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CLK operating current.

7. After power down mode, no CLK operating current.

8. After self refresh mode set, self refresh current.

9. Input signals are VIH or VIL fixed.

Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)

Parameter

Symbol

Min

Max

Unit

Notes

Input capacitance (CLK)

CI1

10

14

pF

1, 2, 4

Input capacitance

CI2

10

14

pF

1, 2, 4

(Input except DQM)

Input capacitance (DQM)

CI3

2.5

5

pF

1, 2, 4

Output capacitance (DQ)

CO

3

5

pF

1, 2, 3, 4

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.

3. DQMB = VIH to disable Dout.

4. This parameter is sampled and not 100% tested.

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