EBD21RD4ABNA-10 查看數據表（PDF） - Elpida Memory, Inc

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EBD21RD4ABNA-10

2GB Registered DDR SDRAM DIMM

Elpida Memory, Inc 

Differential Clock Net Wiring (CK0, /CK0)

0ns (nominal)

PLL

OUT1

CK0

/CK0

120Ω

IN

120Ω

OUT'N'

C

Feedback

EBD21RD4ABNA

SDRAM

stack

SDRAM

stack

240Ω

Register

120Ω

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0 ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

in a similar manner.

4. Termination resistors for feedback path clocks are located after the pins of the PLL.

Preliminary Data Sheet E0273E20 (Ver. 2.0)

9

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