![](/html/AMD/278838/page173.png)
VIH
CS
VIL
tCSS
1 µs (1)
tSKH
tSKL
VIH
SK
VIL
VIH
DI
VIL
VOH
DO (READ)
VOL
VOH
DO (PROGRAM)
VOL
tDIS
tDIH
tPDO
tSV
tPDI
Status Valid
Note:
1. This is the minimum SK period.
Typical XXC56 Series
Serial EEPROM Control Timing
AMD
tCSH
tDF
tDF
18183B-57
Am79C961
1-647