APU3073 查看數據表（PDF） - Advanced Power Electronics Corp

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APU3073

SYNCHRONOUS PWM CONTROLLER WITH OVER-CURRENT PROTECTION / LDO CONTROLLER

Advanced Power Electronics Corp 

APU3073

VDS

90%

10%

VGS

td(ON)

tr td(OFF)

tf

Figure 9 - Switching time waveforms.

The output LC filter introduces a double pole, –40dB/

decade gain slope above its corner resonant frequency,

and a total phase lag of 1808 (see Figure 10). The Reso-

nant frequency of the LC filter is expressed as follows:

1

FLC = 2p3 LO3CO

---(13)

Figure 10 shows gain and phase of the LC filter. Since

we already have 1808 phase shift just from the output

filter, the system risks being unstable.

Gain

Phase

From IRF7832 data sheet we obtain:

IRF7832

tr = 12.3ns

tf = 21ns

These values are taken under a certain condition test.

For more details please refer to the IRF7832 datasheet.

By using equation (12), we can calculate the total switch-

ing losses.

PSW(TOTAL) = 133mW

Programming the Over-Current Limit

The over-current threshold can be set by connecting a

resistor (RSET) from drain of low side MOSFET to the

OCSet pin. The resistor can be calculated by using equa-

tion (2).

The RDS(ON) has a positive temperature coefficient and it

should be considered for the worse case operation.

RDS(ON) = 4mV31.5 = 6mV

ISET ≅ IO(LIM) = 8A31.5 = 12A

(50% over nominal output current)

This results to: RSET ≅ 4.8KV

Select: RSET = 5KV

Feedback Compensation

The APU3073 is a voltage mode controller; the control

loop is a single voltage feedback path including error

amplifier and error comparator. To achieve fast transient

response and accurate output regulation, a compensa-

tion circuit is necessary. The goal of the compensation

network is to provide a closed loop transfer function with

the highest 0dB crossing frequency and adequate phase

margin (greater than 458).

0dB

08

-40dB/decade

-1808

FLC Frequency

FLC Frequency

Figure 10 - Gain and phase of LC filter.

The APU3073’s error amplifier is a differential-input

transconductance amplifier. The output is available for

DC gain control or AC phase compensation.

The E/A can be compensated with or without the use of

local feedback. When operated without local feedback,

the transconductance properties of the E/A become evi-

dent and can be used to cancel one of the output filter

poles. This will be accomplished with a series RC circuit

from Comp pin to ground as shown in Figure 11.

Note that this method requires that the output capacitor

should have enough ESR to satisfy stability requirements.

In general, the output capacitor’s ESR generates a zero

typically at 5KHz to 50KHz which is essential for an

acceptable phase margin.

The ESR zero of the output capacitor expressed as fol-

lows:

FESR

=

1

2p3ESR3Co

---(14)

10/17

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