APW7061 查看數據表（PDF） - Anpec Electronics

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APW7061

Synchronous Buck PWM Controller

Anpec Electronics 

APW7061

Functional Pin Description

VCC (Pin 1)

COMP (Pin 3)

This pin provides a supply voltage to the device, When

VCC is rising above the threshold 4.2V, the device is

turned on, and convers ely, when V CC drops below

the falling threshold, the device is turned off. A 1uF

decoupling capacitor to GND is recommended.

FB (Pin 2)

FB pin is the inverting input of the error amplifier, and

it receives the feedback voltage from an external

resistive divider across the output (VOUT). The output

voltage is determined by:

VOUT

=

0.8V × 1+

ROUT

RGND



where ROUT is the resistor connected from VOUT to FB,

and RGND is the resistor connected from FB to GND.

When the FB voltage is under 50% VREF, it will cause

the under voltage protection, and shutdown the device.

Remove t he condit ion and restart the VCC voltage,

will enable again the device.

This pin is the output of the error amplifier. Add an

ex ternal resist or and capacitor net work to provide

the loop c ompensation for the P WM c onverter (s ee

Applicat ion Informat ion).

Pull this pin below 0.4V will shutdown t he controller,

forcing the UGATE and LGATE signals to be 0V. A

soft st art c ycle will be init iated upon the release of

this pin.

PHASE (Pin 5)

A resistor (ROCSET) is connected between this pin and

the drain of the low-side MOSFET will determine the

over current limit. A n int ernally generated 250uA

current source will flow through this resistor, creating

a voltage drop. This voltage will be compared with the

voltage across the low-side MOSFET. The threshold

of the over current limit is therefore given by :

ILIMIT

= 250 µ A × R OCSET

R DS(ON)

GND (Pin 4)

Signal ground for the IC.

UGATE (Pin 6)

This pin provides gate drive for the high-side MOSFET.

BOOT (Pin 7)

An over current condit ion will cy cle the soft s tart

funct ion unt il the over current condition is removed.

Because of the comparator delay time, so the on time

of the low-side MOSFET must be longer than 800ns

to have the over current protection work.

This pin provides the supply voltage to the high side

MOS FE T driver. For driving logic level N-channel

MOSEFT, a boots trap circuit can be use to create a

suitable driver’s supply.

LGATE (Pin 8)

This pin provides the gate drive signal for the low side

MOSFET.

C opyright © ANPEC Electronics C orp.

5

Rev. A.7 - Nov., 2005

www.anpec.com.tw

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