APW7068 查看數據表（PDF） - Anpec Electronics

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APW7068

Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage

Anpec Electronics 

APW7068

Function Pin Descriptions

VCC12

Power supply input pin. Connect a nominal 12V power

supply to this pin. The power-on reset function monitors

the input voltage at this pin. It is recommended that a

decoupling capacitor (1 to 10µF) be connected to GND

for noise decoupling.

BOOT

This pin provides the bootstrap voltage to the upper

gate driver for driving the N-channel MOSFET. An

external capacitor from PHASE to BOOT, an internal

diode, and the power supply valtage VCC12, generates

the bootstrap voltage for the upper gate diver (UGATE).

PHASE

This pin is the return path for the upper gate driver.

Connect this pin to the upper MOSFET source, and

connect a capacitor to BOOT for the bootstrap voltage.

This pin is also used to monitor the voltage drop across

the lower MOSFET for over-current protection.

GND

This pin is the signal ground pin. Connect the GND pin

to a good ground plane.

PGND

This pin is the power ground pin for the lower gate

driver. It should be tied to GND pin on the board.

COMP

This pin is the output of PWM error amplifier. It is used

to set the compensation components.

FB

This pin is the inverting input of the PWM error amplifier.

It is used to set the output voltage and the compensation

components. This pin is also monitored for over-voltage

protection. When the FB voltage is over 135% of

reference voltage, the controller will make Low-side

gate signal fully turn on until the fault events are

removed.

LGATE

This pin is the gate driver for the lower MOSFET of

PWM output.

DRIVE

This pin drives the gate of an external N-channel

MOSFET for linear regulator. It is also used to set the

compensation for some specific applications,for

example, with low values of output capacitance and

ESR.

FBL

This pin is the inverting input of the linear regulator

error amplifier. It is used to set the output voltage.

This pin is also monitored for under-voltage protection.

When the FBL voltage is under 50% of reference

voltage (0.4V), both outputs will be shutdown

immediately.

OCSET

Connect a resistor (Rocset) from this pin to GND, an

internal 40uA current source will flow through this

resistor and create a voltage drop. When VCC12

reaches the POR rising threshold voltage, the voltage

drop of Rocset will be memoried and compared with

the voltage across the lower MOSFET. The threshold

of the over current limit is therefore given by:

I = LIMIT

I × R OCSET

OCSET

R (L DS(ON) OW − Side)

REF_OUT

This pin provides a buffed voltage, which is from internal

reference voltage. It is recommended that a 1uF

capacitor is connected to ground for stability.

FS_DIS

This pin provides shutdown function. Use an open drain

logic signal to pull this pin low to disable both outputs,

leave open to enable both outputs.

UGATE

This pin is the gate driver for the upper MOSFET of

PWM output.

Copyright © ANPEC Electronics Corp.

7

Rev. A.2 - Jun., 2006

www.anpec.com.tw

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