AS1545-BQFT 查看數據表（PDF） - austriamicrosystems AG

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AS1545-BQFT

Dual, 12-Bit, 1MSPS, SAR ADC

austriamicrosystems AG 

AS1545

Datasheet - Pinout

Table 1. Pin Description

Pin Number

Pin Name

13 to 18

BIN0 to BIN5

21

RANGE

22

23 to 25

26

27

SGL/DIFF

A2 to A0

CSN

SCLK

28, 30

DOUTB, DOUTA

31

VDRIVE

32

DVDD

33

Exp. Pad

Description

Analog Inputs of ADC B. These may be programmed as six single-ended

channels, three pseudo-differential or three true-differential analog input

channel pairs. (see Table 5 on page 20).

Analog Input Range Selection. Logic input. The polarity on this pin

determines the input range of the analog input channels. If this pin is tied to

a logic low, the analog input range is 0V to VREF. If this pin is tied to a logic

high when CSN goes low, the analog input range is 2 × VREF.

Logic Input. This pin selects whether the analog inputs are configured as

differential pairs or single ended. A logic low selects differential operation

while a logic high selects single-ended operation.

Multiplexer Select. Logic inputs. These inputs are used to select the pair of

channels to be simultaneously converted, such as Channel 1 of both ADC A

and ADC B, Channel 2 of both ADC A and ADC B, and so on.

Chip Select. Active low logic input. This input provides the dual function of

initiating conversions on the AS1545 and framing the serial data transfer.

Serial Clock Input. A serial clock input provides the SCLK for accessing the

data from the AS1545. This clock is also used as the clock source for the

conversion process.

Serial Data Outputs. The data output is supplied to each pin as a serial

data stream. The bits are clocked out on the falling edge of the SCLK input

and 15 SCLKs are required to access the data. The data simultaneously

appears on both pins from the simultaneous conversions of both ADCs. The

data stream consists of three leading zeros followed by the 12 bits of

conversion data. The data is provided MSB first. If CSN is held low for 16

SCLK cycles rather than 15, then single trailing zero appears after the 12bits

of data. If CSN is held low for a further 16 SCLK cycles on either DOUTA or

DOUTB, futher data is clocked out according to the timing diagram.

Logic Power Supply Input. The voltage supplied at this pin determines at

what voltage the interface operates. This pin should be decoupled to DGND.

The voltage at this pin may be different than that at AVDD and DVDD but

should never exceed either by more than 0.3V.

Digital Supply Voltage. 2.7V to 5.25V. This is the supply voltage for all

digital circuitry on the AS1545. The DVDD and AVDD voltages should ideally

be at the same potential and must not be more than 0.3V apart even on a

transient basis. This supply should be decoupled to DGND.

Exposed Pad. This pin can be not connected or connected AGND. The

exposed pad must not be connected to VDD.

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Revision 1.01

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