AS6C6264-55STCN 查看數據表（PDF） - Alliance Semiconductor

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AS6C6264-55STCN

8K X 8 BIT LOW POWER CMOS SRAM

Alliance Semiconductor 

®

8K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS

PARAMETER

VCC for Data Retention

Data Retention Current

Chip Disable to Data

Retention Time

Recovery Time

tRC* = Read Cycle Time

SYMBOL

TEST CONDITION

VDR

CE# ≧ VCC - 0.2V

or CE2 ≦ 0.2V

VCC = 1.5V

IDR CE# ≧ VCC - 0.2V

or CE2 ≦ 0.2V

tCDR

See Data Retention

Waveforms (below)

tR

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE# controlled)

Vcc

CE#

Vcc(min.)

tCDR

VIH

VDR ≧ 1.5V

CE# ≧ Vcc-0.2V

MIN.

1.5

-

0

tRC*

TYP.

-

0.5

-

-

MAX.

5.5

UNIT

V

10

µA

-

ns

-

ns

Vcc(min.)

tR

VIH

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Vcc

CE2

Vcc(min.)

tCDR

VIL

VDR ≧ 1.5V

CE2 ≦ 0.2V

Vcc(min.)

tR

VIL

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