AS6C62256 查看數據表（PDF） - Alliance Semiconductor

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AS6C62256

32K X 8 BIT LOW POWER CMOS SRAM

Alliance Semiconductor 

February 2007

AS6C62256

®

32K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

Address

CE#

WE#

Dout

tWC

tAW

tCW

tAS

tWP

tWHZ

(4)

Din

tWR

TOW

High-Z

(4)

tDW

tDH

Data Valid

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

Address

CE#

WE#

Dout

tAS

tWHZ

(4)

tWC

tAW

tCW

tWP

Din

tWR

High-Z

tDW

tDH

Data Valid

Notes :

1.WE#, CE# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#.

3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.

6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

02/FEB/07, v1.0

Alliance Memory Inc.

Page 6 of 12

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