AS7C1024C-12JIN 查看數據表（PDF） - Alliance Semiconductor
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AS7C1024C-12JIN Datasheet PDF : 9 Pages
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AS7C1024C
®
Read cycle (over the operating range)3,9
Parameter
Read cycle time
Address access time
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change
CE1 Low to output in low Z
CE2 High to output in low Z
CE1 Low to output in high Z
CE2 Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
Power down time
Key to switching waveforms
Rising input
Symbol
tRC
tAA
tACE1
tACE2
tOE
tOH
tCLZ1
tCLZ2
tCHZ1
tCHZ2
tOLZ
tOHZ
tPU
tPD
Falling input
AS7C1024C-12
Min
Max
Unit
12
–
ns
–
12
ns
–
12
ns
–
12
ns
–
6
ns
4
–
ns
3
–
ns
3
–
ns
0
6
ns
–
5
ns
0
–
ns
–
5
ns
0
–
ns
–
12
ns
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
DOUT
tOH
Data valid
Notes
3
3, 12
3, 12
5
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
4, 5
4, 5, 12
4, 5, 12
Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12
CE1
tRC1
CE2
tOE
OE
tOLZ
tOHZ
DOUT
tACE1, tACE2
Data valid
tCHZ1, tCHZ2
Current
supply
tCLZ1, tCLZ2
tPU
50%
tPD
ICC
50%
ISB
12/5/06, v. 1.0
Alliance Memory
P. 4 of 9
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