AS7C34096A 查看數據表（PDF） - Alliance Semiconductor
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AS7C34096A Datasheet PDF : 9 Pages
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Write waveform 2 (CE controlled)10
Address
CE
WE
DIN
tWC
tAW
tAS
tCW
tWP
tWZ
DOUT
tWR
tAH
tDW
tDH
Data valid
AS7C34096A
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figures A and B.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
DOUT
+3.3V
+3.0V
90%
90%
10%
10%
GND
2 ns
Figure A: Input pulse
DOUT
350Ω
320Ω
C11
GND
Figure B: 3.3V Output load
Thevenin equivalent:
168Ω
+1.728V
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4 tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6 WE is HIGH for read cycle.
7 CE and OE are LOW for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 All write cycle timings are referenced from the last valid address to the first transitioning address.
11 C=30pF, except on High Z and Low Z parameters, where C=5pF.
8/17/04, v. 2.1
Alliance Semiconductor
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