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80C54 查看數據表(PDF) - Atmel Corporation

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产品描述 (功能)
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80C54 Datasheet PDF : 62 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Features
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/machine cycle)
– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
– 60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes, 32K-bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Hardware Watchdog Timer (One-time enabled with Reset-Out)
Asynchronous port reset
Interrupt Structure with
6 Interrupt sources
4 level priority interrupt system
Full duplex Enhanced UART
Framing error detection
Automatic address recognition
Low EMI (inhibit ALE)
Power Control modes
Idle mode
Power-down mode
Power-off Flag
Once mode (On-chip Emulation)
Power supply: 4.5-5.5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 F1, CQPJ44 (window), CDIL40
(window)
8-bit CMOS
Microcontroller
16/32 Kbytes
ROM/OTP
TS80C54/58X2
TS87C54/58X2
AT80C54/58X2
AT87C54/58X2
1. Description
TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the
80C51 CMOS single chip 8-bit microcontroller.
The TS80C54/58X2 retains all features of the Atmel 80C51 with extended
ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/counters.
In addition, the TS80C54/58X2 a Hardware Watchdog Timer, a more versatile serial
channel that facilitates multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C54/58X2 allows to reduce system power consump-
tion by bringing the clock frequency down to any value, even DC, without loss of data.
Rev. 4431E–8051–04/06

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