SP708REP 查看數據表（PDF） - Exar Corporation

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SP708REP

+3.0V/+3.3V low power microprocessor supervisory circuits

Exar Corporation 

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

MANUAL RESET

The manual-reset input (MR) allows RESET to

be triggered by a pushbutton switch. The switch

is effectively debounced by the 140ms

minimum RESET pulse width. MR is TTL/CMOS

logic compatible, so it can be driven by an

external logic line. MR can be used to force a

watchdog timeout to generate a RESET pulse in

the SP706R/S/T-SP708R/S/T. Simply connect

WDO to MR.

Fig. 19: Timing Diagrams with WDI tri-stated.

POWER-FAIL COMPARATOR

The power-fail comparator can be used for

various purposes because its output and non

inverting input are not internally connected.

The inverting input is internally connected to a

1.25V reference.

To build an early-warning circuit for power

failure, connect the PFI pin to a voltage divider

as shown in Figure 20. Choose the voltage

divider ratio so that the voltage at PFI falls

below 1.25V just before the +5V regulator

drops out. Use PFO to interrupt the µP so it can

prepare for an orderly power-down.

Ensuring a Valid Reset Output Down to

VCC=0V

When VCC falls below 1V, the RESET output no

longer sinks current, it becomes an open circuit.

High-impedance CMOS logic inputs can drift to

undetermined voltages if left undriven. If a pull-

down resistor is added to the RESET pin, any

stray charge or leakage currents will be shunted

to ground, holding RESET LOW. The resistor

value is not critical. It should be about 100KΩ,

large enough not to load RESET and small

enough to pull RESET to ground.

MONITORING VOLTAGES OTHER THAN THE

UNREGULATED DC INPUT

Monitor voltages other than the unregulated DC

by connecting a voltage divider to PFI and

adjusting the ratio appropriately. If required,

add hysteresis by connecting a resistor (with a

value approximately 10 times the sum of the

two resistors in the potential divider network)

between PFI and PFO. A capacitor between PFI

and GND will reduce the power-fail circuit's

sensitivity to high-frequency noise on the line

being monitored. RESET can be used to monitor

voltages other than the +3.3V/+3.0V VCC line.

Connect PFO to MR to initiate a RESET pulse

when PFI drops below 1.25V. Figure 21 shows

the SP706R/S/T-SP708R/S/T series configured

to assert RESET when the +3.3V/3.0V supply

falls below the RESET threshold, or when the

+12V supply falls below approximately 11V.

Fig. 20: Typical Operating Circuit

© 2015 Exar Corporation

MONITORING A NEGATIVE VOLTAGE SUPPLY

The power-fail comparator can also monitor a

negative supply rail, shown in Figure 22. When

the negative rail is good (a negative voltage of

large magnitude), PFO is LOW. By adding the

resistors and transistor as shown, a HIGH PFO

12/17

Rev. 3.0.0

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