AV3842A 查看數據表（PDF） - Avic Technology
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AV3842A Datasheet PDF : 6 Pages
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@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
OSCILLATOR SECTION
8
4
5
Large RT
Small CT
RT
CT Small RT
Large CT
V4
INTERNAL
CLOCK
V4
INTERNAL
CLOCK
100
td (µs)
10
1
0.1
1
Dead time VS CT(RT>5kΩ) Timing Resistance Vs Frequency
10
100
CT (nF)
100
RT (kΩ)
CT=1nF
CT=2.2nF
CT=4.7nF
10
CT=10nF
CT=22nF
CT=47nF
CT=100nF
1
10 2
103
104
105
10 6
Frequency (Hz)
SHUTDOWN TECHNIQUES
1kΩ
8
1
Shutdown
Shutdown
3
To current
Sense resistor
Shutdown UTC UC3842A can be
accomplished by two methods; either raise pin 3
above 1V or pull Pin 1 below a voltage two diode
drops above ground. Either method caused the
output of PWM comparator to be high(refer to
block diagram).The PWM latch is reset dominant
so that the output will remain low until the next
clock cycle after the shutdown condition at pins 1
and/or 3 is removed . In one example, an
externally latched shut –down may be
accomplished by adding an SCR which be reset
by cycling Vcc below the lower UVLO threshold.
At this point the reference turns off allowing the
SCR to reset.
QW-R103-002,B
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