WED9LAPC2C16V8BC 查看數據表（PDF） - White Electronic Designs => Micro Semi
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WED9LAPC2C16V8BC Datasheet PDF : 24 Pages
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White Electronic Designs WED9LAPC2C16V8BC
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Current State
Refreshing
Mode Register
Accessing
VCRAS#
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
VCCAS#
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
VCWE#
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Command
VCBS VCADDR
OP Code
X
X
X
X
BA Row Address
BA
Column
BA
Column
X
X
X
X
OP Code
X
X
X
X
BA Row Address
BA
Column
BA
Column
X
X
X
X
Description
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Action
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
Notes
Notes:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if VCBS selects this bank then the action is illegal. If VCBS selects the bank not being referenced by the Current State
then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The VCRAS# to VCCAS# Delay (tRCD) must occur before the command is given.
5. Address VCADDR9/AP is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank-to-bank delay time (tRRD) is not
satisfied.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2000
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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