VP310 查看數據表（PDF） - Mitel Networks

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VP310

Satellite Channel Decoder

Mitel Networks 

VP310

PRELIMINARY DATA

An internal state machine that handles all the demodulator functions controls the signal tracking

and acquisition. Various pre-set modes are available as well as blind acquisition where the

receiver has no prior knowledge of the received signal. Fast acquisition algorithms have been

provided for low Symbol rate applications. Full interactive control of the acquisition function is

possible for debug purposes.

In the event of a signal fade or a cycle slip, QPSK demodulator allows sufficient time for the FEC

to re-acquire lock, for example, via a phase rotation in the Viterbi decoder. This is to minimise the

loss of signal due to the signal fade. Only if the FEC fails to re-acquire lock for a long period

(which is programmable) would QPSK try to re-acquire the signal.

The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with

DSS and DVB standards. Although not a part of the DVB standard, VP310 allows a roll-off of

0.20 to be used with other DVB parameters.

An AGC signal is provided to control the signal levels in the tuner section of the receiver and

ensure the signal level fed to the VP310 is set at an optimal value under all reception conditions.

The VP310 provides comprehensive information on the input signal and the state of the various

parts of the device. This information includes Signal to Noise Ratio (SNR), signal level, AGC

lock, timing and carrier lock signals. A maskable interrupt output is available to inform the host

controller when events occur.

1.4 Forward Error Correction

The VP310 contains FEC blocks to enable error correction for DVB-S and DSS transmissions.

The Viterbi decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or

7/8. The block features automatic synchronisation and automatic code rate detection. The trace

back depth of 128 provides better performance at high code rates and the built-in synchronisation

algorithm allows the Viterbi decoder to lock onto signals with very poor signal-to-noise ratios.

Viterbi bit error rate monitor provides an indication of the error rate at QPSK output.

The 24-bit error count register in the Viterbi decoder allows the bit error rate at the output of the

QPSK demodulator to be monitored. The 24-bit bit error count register in the Reed-Solomon

decoder allows the Viterbi output bit error rate to be monitored. The 16-bit uncorrectable packet

counter yields information about the output packet error rate. These three monitors and the

QPSK SNR register allows the performance of the device and its individual components, such as

the QPSK demodulator and the Viterbi decoder, to be monitored extensively by the external

microprocessor.

The frame/byte align block features a sophisticated synchronisation algorithm to ensure reliable

recovery of DVB and DSS framed data streams under worst case signal conditions. The de-

interleaver uses on-chip RAM and is compatible with the DVB and DSS algorithms.

The Reed-Solomon decoder is a truncated version of the (255, 239) code. The code block size is

204 for DVB and 146 for DSS. The decoder provides a count of the number of uncorrectable

blocks as well as the number of bit errors corrected. The latter gives an indication of the bit error

rate at the output of the Viterbi decoder.

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