CMX641AD2 查看數據表（PDF） - CML Microsystems Plc

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CMX641AD2

DUAL SPM/SECURITY DETECTOR/GENERATOR

CML Microsystems Plc 

Dual SPM/Security Detector/Generator

Package Package

D2

P4

Signal

Pin No.

18

Pin No.

18

Name

Type

PRESET

LEVEL

TONE ASK

Description

CMX641A

This is a dual function pin differing between

Fixed Bandwidth Operating state and Enhanced

Features Operating state.

This input has an internal pullup resistor on chip

so that the default (open circuit) modes are

Fixed Sensitivity (Fixed Bandwidth Operating

state) and No Tone (Enhanced Features

Operating state).

(Fixed Bandwidth Operating state).

A logic input to set the sensitivity mode of the

CMX641A. When high (logic ‘1’), both channels

are in the Fixed Sensitivity mode. The external

components govern the input sensitivity; the

SYSTEM SELECT pin selects 12kHz or 16kHz

operation.

When low logic (logic ‘0’), the system frequency

and sensitivity of both channels are in the

Controlled Sensitivity mode. Device

sensitivities and system selection are via the

CHIP SELECTN/SERIAL DATA/SERIAL

CLOCK inputs.

(Enhanced Features Operating state).

A logic input used to ASK modulate the TONE

OP pin. A logic high corresponds to no tone

and a logic low to tone.

19

19

CHIP

I/P

The serial data pins for use in data loading when

SELECTN

using the CMX641A in Controlled Sensitivity

20

20

SERIAL

I/P

mode (Fixed Bandwidth Operating state) or in

CLOCK

21

21

SERIAL

DATA

Enhanced Features Operating state (See

I/P

Figures 7 & 8). When the device is in Fixed

Sensitivity mode (Fixed Bandwidth Operating

state), these pins should be connected to VSS or

VDD.

© 2002 Consumer Microcircuits Limited

6

D/641A/5

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