CXD1261 查看數據表（PDF） - Sony Semiconductor

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CXD1261

Sync Signal, Timing Signal Generator for CCD Cameras

Sony Semiconductor 

CXD1261AR

ED2

tS2

th2

ED1

tS1

tS0

ED0

tW0

Symbol

Min. Max.

tS2 ED2 setup time against the rising edge of ED1

20ns —

th2 ED2 hold time against the rising edge of ED1

20ns —

tS1 ED1 rising setup time against the rising edge of ED0

20ns —

tWO ED0 pulse width

20ns 50µs

tSO ED0 rising setup time against the rising edge of ED1

20ns —

<Shutter speed calculation> (During frame accumulation, low-speed shutter does not operate normally.)

High-speed shutter

• For EIA

T = [26210 – (1FF16 – L16) ] × 63.56 + 34.78µs ∗ L16: load value

• For CCIR

T = [31210 – (1FF16 – L16) ] × 64 + 35.6µs

EIA

CCIR

Load value Shutter speed Calculated value Load value Shutter speed Calculated value

0FA16

1/10000

1/10169

0C816

1/1000

1/10040

0FC16

1/4000

1/4435

0CA16

1/4000

1/4394

10016

1/2000

1/2085

0CE16

1/2000

1/2068

10816

1/1000

1/1012

0D616

1/1000

1/1004

11816

1/500

1/499

0E616

1/500

1/495

13716

1/250

1/252

10516

1/250

1/250

17616

1/125

1/125

14316

1/125

1/125

19616

1/100

1/100

14916

1/100

1/120

Low-speed shutter (Does not operate normally during frame accumulation.)

N = 2 × (1FF16 – L16) FLD

However, 1FF cannot be used as the load value.

Load value Shutter speed (FLD)

1FE16

2

1FD16

4

:

:

10116

508

10016

510

– 10 –

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