CXD2422R 查看數據表（PDF） - Sony Semiconductor

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CXD2422R

CCD Camera Timing Generator

Sony Semiconductor 

CXD2422R

Phases of SHP, SHD, and XRG pulses can be adjusted using on-chip buffers.

Internal CXD2422R

SHP

R

15

BAI

16

BAO

17

C

SHP

Delay times of SHP, SHD, and XRG can be adjusted with C and R.

Delay characteristics of on-chip buffers (VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF)

Symbol

Definition

Min. Typ. Max. Unit

tpd16

tpd17

tpd18

tpd19

tpd20

tpd21

Rising delay time from BAI to BAO

Falling delay time from BAI to BAO

Rising delay time from BBI to BBO

Falling delay time from BBI to BBO

Rising delay time from BCI to BCO

Falling delay time from BCI to BCO

4.0 7.1 13.9 ns

2.8 5.5 10.7 ns

4.0 7.0 13.8 ns

3.0 5.4 10.7 ns

4.3 7.6 15.0 ns

3.4 6.0 11.7 ns

3) I/O pin capacitances

Item

Input pin capacitance

Output pin capacitance

Symbol

CIN

COUT

(VDD = VI = 0V, f = 1MHz)

Min. Typ. Max. Unit

9 pF

11 pF

–8–

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