CY2318ANZ 查看數據表（PDF） - Cypress Semiconductor
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CY2318ANZ Datasheet PDF : 9 Pages
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Switching Characteristics[4]
Parameter
Name
Maximum Operating Frequency
Duty Cycle[3, 5] = t2 ÷ t1
t3
Rising Edge Rate[3]
t4
Falling Edge Rate[3]
t5
Output to Output Skew[3]
t6
SDRAM Buffer LH Prop. Delay[3]
t7
SDRAM Buffer HL Prop. Delay[3]
t8
SDRAM Buffer Enable Delay[3]
t9
SDRAM Buffer Disable Delay[3]
Test Conditions
Measured at 1.5V
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
CY2318ANZ
Min. Typ. Max. Unit
100 MHz
45.0 50.0 55.0
%
0.9
1.5
4.0
V/ns
0.9
1.5
4.0
V/ns
150
250
ps
1.0
3.5
5.0
ns
1.0
3.5
5.0
ns
1.0
5
12
ns
1.0
20
30
ns
Switching Waveforms
Duty Cycle Timing
1.5V
t1
t2
1.5V
1.5V
All Outputs Rise/Fall Time
2.4V
OUTPUT 0.4V
t3
2.4V
0.4V
t4
3.3V
0V
Output-Output Skew
OUTPUT
1.5V
OUTPUT
t5
1.5V
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Document #: 38-07181 Rev. *B
Page 5 of 9
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