CY7B9910 查看數據表（PDF） - Cypress Semiconductor

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CY7B9910

Low Skew Clock Buffer

Cypress Semiconductor 

CY7B9910

CY7B9920

Operational Mode Descriptions

Figure 2 shows the device configured as a zero skew clock

buffer. In this mode the 7B9910/9920 is used as the basis for a

low skew clock distribution tree. The outputs are aligned and may

each drive a terminated transmission line to an independent

load. The FB input is tied to any output and the operating

frequency range is selected with the FS pin. The low skew speci-

fication, coupled with the ability to drive terminated transmission

lines (with impedances as low as 50 ohms), enables efficient

printed circuit board design.

Figure 1 shows the CY7B9910/9920 connected in series to

construct a zero skew clock distribution tree between boards.

Cascaded clock buffers accumulates low frequency jitter

because of the non-ideal filtering characteristics of the PLL filter.

Do not connect more than two clock buffers in series.

Figure 3. Board-to-Board Clock Distribution

SYSTEM

CLOCK

REF

FB

REF

FS

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

TEST

LOAD

Z0

LOAD

Z0

LOAD

Z0

FB

REF

FS

Z0

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

TEST

LOAD

LOAD

Document Number: 38-07135 Rev. *B

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