7C10211B-10(2004) 查看數據表（PDF） - Cypress Semiconductor
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7C10211B-10 Datasheet PDF : 10 Pages
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Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [13, 14]
tWC
ADDRESS
CE
tSA
WE
BHE, BLE
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
ADDRESS
tAW
tWC
tSCE
tPWE
tBW
tSD
BHE, BLE
tSA
tBW
tAW
tPWE
WE
tSCE
CE
tSD
DATA I/O
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE or BHE and/or BLE= VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
CY7C1021B
CY7C10211B
tHA
tHD
tHA
tHD
Document #: 38-05145 Rev. *A
Page 6 of 10
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