7C1021B-12 查看數據表（PDF） - Cypress Semiconductor
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7C1021B-12 Datasheet PDF : 10 Pages
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CY7C1021B
AC Test Loads and Waveforms
R 481Ω
5V
R 481Ω
5V
OUTPUT
OUTPUT
30 pF
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
INCLUDING
JIG AND
SCOPE
(b)
167
Equivalent to: THÉVENIN OUTPUT
EQUIVALENT
30 pF
R2
255Ω
1.73V
3.0V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
Fall Time: 1 V/ns
Switching CharacteristicsOver the Operating Range[5]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[8]
tWC
tSCE
tAW
tHA
tSA
tSD
tHD
tLZWE
tHZWE
tBW
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6, 7]
Byte Enable to End of Write
7C1021B-12
Min.
Max.
12
12
3
12
6
0
6
3
6
0
12
6
0
6
12
9
8
0
0
6
0
3
6
8
7C1021B-15
Min.
Max.
Unit
15
ns
15
ns
3
ns
15
ns
7
ns
0
ns
7
ns
3
ns
7
ns
0
ns
15
ns
7
ns
0
ns
7
ns
15
ns
10
ns
10
ns
0
ns
0
ns
8
ns
0
ns
3
ns
7
ns
9
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05145 Rev. *C
Page 4 of 10
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