CY7C1212F 查看數據表（PDF） - Cypress Semiconductor

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CY7C1212F

1-Mbit (64K x 18) Pipelined Sync SRAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle Timing[17, 18]

tCYC

CY7C1212F

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

GW

CE

tCH tCL

tADS tADH

tADS tADH

tAS tAH

A1

A2

Byte write signals are

ignored for first cycle when

ADSP initiates burst

tCES tCEH

ADV

OE

Data In (D)

Data Out (Q)

tDS tDH

High-Z

t

OEHZ

D(A1)

BURST READ

Single WRITE

D(A2)

tWES tWEH

ADSC extends burst

tADS tADH

A3

tWES tWEH

ADV suspends burst

t

ADVS

tADVH

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note:

18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A : B] LOW.

Document #: 38-05423 Rev. *A

Page 11 of 15

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