CY7C1215F 查看數據表（PDF） - Cypress Semiconductor
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CY7C1215F Datasheet PDF : 16 Pages
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CY7C1215F
Truth Table[2, 3, 4, 5, 6, 7]
Next Cycle
Add. Used ZZ CE3 CE2 CE1
Unselected
None
L XX
H
ADSP ADSC ADV
X
L
X
OE
DQ
Write
X Three-State X
Unselected
None
L HX
L
L
X
X
X Three-State X
Unselected
None
L XL
L
L
X
X
X Three-State X
Unselected
None
L HX
L
H
L
X
X Three-State X
Unselected
None
L XL
L
H
L
X
X Three-State X
Begin Read
External
L
LH
L
L
X
X
X Three-State X
Begin Read
External
L
LH
L
H
L
X
X Three-State Read
Continue Read Next
L XX
X
H
H
L
H Three-State Read
Continue Read Next
L XX
X
H
H
L
L DQ
Read
Continue Read Next
L XX
H
X
H
L
H Three-State Read
Continue Read Next
L XX
H
X
H
L
L DQ
Read
Suspend Read Current
L XX
X
H
H
H
H Three-State Read
Suspend Read Current
L XX
X
H
H
H
L DQ
Read
Suspend Read Current
L XX
H
X
H
H
H Three-State Read
Suspend Read Current
L XX
H
X
H
H
L DQ
Read
Begin Write
Current
L XX
X
H
H
H
X Three-State Write
Begin Write
Current
L XX
H
X
H
H
X Three-State Write
Begin Write
External
L
LH
L
H
H
X
X Three-State Write
Continue Write Next
L XX
X
H
H
H
X Three-State Write
Continue Write Next
L XX
H
X
H
H
X Three-State Write
Suspend Write Current
L XX
X
H
H
H
X Three-State Write
Suspend Write Current
L XX
H
X
H
H
X Three-State Write
ZZ “Sleep”
None
H XX
X
X
X
X
X Three-State X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD),BWE, GW=H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE
is a don't care for the remainder of the Write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05421 Rev. **
Page 6 of 16
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